1. Field of the Invention
The present invention relates to the improvement of an erroneous write (or erase) operation preventing circuit in a semiconductor memory device such as an electrically erasable and programmable read-only memory (E.sup.2 PROM), a nonvolatile random access memory (NOVRAM), and the like.
2. Description of the Related Art
In an E.sup.2 PROM, NOVRAM, and the like, a write/erase voltage, which is remarkably higher than a normal power supply voltage V.sub.CC (for example, 5 V), is required. For this purpose, a step-up circuit has been incorporated into each chip to generate an internal write/erase voltage IVP such as 20 to 25 V. That is, a write/erase mode, a write enable signal is supplied to the step-up circuit, thereby increasing the write/erase voltage IVP. As a result, this high voltage IVP is applied to a memory cell to perform a write/erase operation thereupon due to a tunneling effect.
However, even when the power supply voltage V.sub.CC is not sufficiently high (for example, lower than 3.5 V), the step-up circuit and other circuits such as address buffers may be operated, thus erroneously carrying out a write/erase operation. That is, when the power supply voltage V.sub.CC rises or falls because the power supply thereof is turned ON or OFF, an erroneous write/erase operation may be carried out, thus destroying data stored in the cells. To avoid this, a V.sub.CC sense circuit is incorporated into each chip for detecting whether or not the power supply voltage V.sub.CC is higher than a predetermined value, and therefore, only when the power supply voltage V.sub.CC is higher than the predetermined value are the step-up circuit and the like operated. An erroneous write/erase operation preventing circuit is conventionally comprised of such a V.sub.CC sense circuit.
In prior art or proposed erroneous write/erase operation preventing circuits, however, the power consumption thereof is relatively large and the configuration thereof is relatively complex, as will be explained later.